The present invention reports a device for scalable inter-nodal communication in a parallel computing system and a parallel computing system incorporating the said device which comprises a Central Processing Unit (CPU) (1) capable of controlling the functions of the device; the said CPU (1) being connected in combination to a Dual Port Memory (DPM) (3), Synchronous Random Access Memory (SRAM) (4), Erasable Programmable Read Only Memory (EPROM) (5) through a Comprehensive Programmable Logic Device (CPLD)(2) capable of interfacing the signals between the said CPU (1) and DPM (3), SRAM (4), EPROM (5); the said CPU (1) and CPLD (2) being also provided in combination conventional peripheral components such as Clock, Clock-Driver, Reset Logic, Baud Rate Generator, Serial communication Controller (SCC), Buffer/Interface and Connector. The device and the computing system is useful for fast communication along with processing for scalable parallel computers and has wide industrial application in software field.