CLOCK-TREE DELAY INDEPENDENT, FAST LOCKING, FULL-DIGITAL DELAY LOCKED LOOP
Application 2597/DEL/2004 published 2006-11-17, filed 2004-12-30
The instant invention provides digital delay locked loop architecture, which is independent of feedback delay (clock tree delay). The architecture employs a frequency detector circuit, which monitors the frequency of input clock and then sets the division factor for the clock going to the control block to have fast locking time, coarse tuning & fine-tuning.
Applicant
1)STMICROELECTRONICS PVT. LTD
:Plot No.2, 3 & 18, Sector 16A, Institutional Area Noida-201 3001, Uttar Pradesh, India Uttar Pradesh India
Inventor
1)ASHISH PANPALIA 2)PUNEET SAREEN
International Info
Classification: H03L7/18