A MEMORY WITH REDUCED BITLINE LEAKAGE CURRENT AND METHOD FOR THE SAME
Application 2614/DEL/2004 published 2006-11-17, filed 2004-12-31
The present invention provides a memory with reduced bitline leakage current and method for same. Reducing bitline leakage current thereby provides more split at sense amplifier node and hence results in more speed. A negative voltage is generated and applied to the access transistors of unselected wordlines which reduces the subthreshold leakage.
Applicant
1)STMICROELECTRONICS PVT. LTD
:PLOT NO.2, 3 & 18, SECTOR 16A, INSTITUTIONAL AREA, NOIDA-201 3001, UTTAR PRADESH, INDIA Uttar Pradesh India
Inventor
1)VIVEK NAUTIYAL
International Info
Classification: G11C11/24