METHOD AND APPARTUS FOR IMPLEMENTING A SELECTIVELY OPERABLE CLOCK BOOSTER FOR DDR.
Application 1871/CHENP/2004 published 2006-06-23, filed 2004-08-23
A method of fabricating a memory module according to one embodiment, a clock booster is mounted on a multi-layer circuit bard (101). The clock booster may be any apparatus that receives a clock input, and output one or more clock signals capable of driving a multiplicity of logic parts without clock distortion. In a preferred embodiment, a phase-locked loop circuit may be used as a clock booster. The test and patching (102) allows a fully-functional memory part adds, it is desirable to only connect the clock signal to those memory parts that are utilized. This may be accomplished using any number of switching mechanisms to connect or disconnect a clock signal to a memory part. In a preferred embodiment, a clock patching network may be used to selectively connect or disconnect outputs of a clock booster to the memory parts (103).
Applicant
CELETRONIX USA,INC. CELETRONIX INTERNATIONAL, LTD.
2125 B Madera Drive, Simi Valey, CA 93065 ,, c/o Codan Services Ltd., Clarendon House, 2 Church Street--Box HM666, Hamilton HM CX,, USA . BERMUDA.
Inventor
International Info
Classification: G06F 19/00
Publication Number:
Priority Information
10/371,736 . 60/360,036 . USA 2003-02-20