PROGRAMMABLE PROCESSOR ARCHITECTURE
Application 113/CHENP/2007 published 2007-08-24, filed 2007-01-11
One embodiment of the present includes a heterogenous. high-performance-scalable processor having at least one W-type sub-processor capable of processing W bits in parallel. W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel. N being an integer value wherein and smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type subprocessor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.
Applicant
1)3PULSI TECHNOLOGY, INC;
:18809 COX AVENUE, SUITE 250, SARATOGA, CA 95070, U.S.A.
Inventor
1)RAMCHANDRAN, AMIT 2)HAUSER, JOHN, REID, JR.,
International Info
Classification: G06F 15/76
Publication Number: WO 2006/017339 A2
Application Date: 2005-07-12
Priority Information
60/587,691 U.S.A. 2004-07-13