BigPatents India

A memory cell array comprising a plurality of memory transistors (1, 2, 3, 4), arranged in a two-dimensional array, each memory transistor having two source/drain areas(14a, 14b, 14c, 14d) which are arranged in a first direction of the memory cell area with a channel substrate area (19) there between, in addition to a gate structure (20) arranged above the channel substrate area (18). The source/drain areas (14a, 14b, 14c, 14d) and the channel substrate areas (18) are formed in a substrate (16) arranged on an insulating layer (12). The channel substrate areas (18) of adjacent memory transistors in the same direction are separated from each other by respective source/drain areas extending as far as the insulating layer (12). The source/drain areas (14a, 14b, 14c, 14d) and the channel substrate areas (18) of memory transistors adjacent in a second direction of the storage cell array are insulated with respect to each other by trenches (30) formed in the substrate (16) filled with an insulating material and extending as far as the insulating layer (12). (FIG. 1)